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9232h-auto-09/14 features supply voltage up to 40v operating voltage v vs = 5v to 28v supply current sleep mode: typically 10a silent mode: typically 47a very low current consumption at low supply voltages (2v < v vs < 5.5v): typically 150a linear low-drop voltage regulator, 85ma current capability: mlc (multi-layer ceramic) capacitor with 0 esr normal, fail-safe, and silent mode atmel ata663454: v cc = 5.0v 2% atmel ata663431: v cc = 3.3v 2% sleep mode: vcc is switched off vcc undervoltage detection with open drain re set output (nres, 4ms reset time) voltage regulator is short-circuit and over-temperature protected adjustable watchdog time via external resistor negative trigger input for watchdog limp home watchdog failure output lin physical layer according to lin 2.0, 2.1, 2.2, 2.2a and saej2602-2 bus pin is overtemperature and short-circuit protected versus gnd and battery high-side switch wake-up capability via lin bus (100s dominant), wkin pin and cl15 pin wake-up source recognition txd time-out timer advanced emc and esd performance fulfills the oem ?hardware requirements for lin in automotive applications rev.1.3? interference and damage protection according to iso7637 qualified according to aec-q100 package: dfn16 with wettable flanks (moisture sensitivity level 1) note: 1. lin sbc: lin system basis chip ata663431/ata663454 lin sbc (1) including lin transceiver, voltage regulator, window watchdog and high-side switch datasheet
ata663431/ata6634 54 [datasheet] 9232h?auto?09/14 2 1. description designed in compliance with lin specifications 2. 0, 2.1, 2.2, 2.2a and saej2602-2, the atmel ? ata663431/ata663454 is a new generation of system basis chips with a fully integrated lin transceiver, a low-dr op voltage regulato r (3.3v/5v/85ma), a window watchdog, and a high-side switch. this combination make s it possible to develop simple, but powerful, slave nodes in lin-bus systems. atmel ata663431/ata663454 is designed to handle low-speed data communication in vehicles (such as in convenience electronics). improved slope control at the lin driver ensures secure data communication up to 20kbaud. the bus output is designed to withstand high voltage. sl eep mode and silent mode gu arantee a minimized current consumption even in the case of a floating or short-circuited lin bus. figure 1-1. block diagram 2 en 4 txd 1 rxd vcc 16 nres 3 gnd 13 short-circuit and overtemperature protection voltage regulator normal/silent/ fail-safe mode 3.3v/5v control unit normal and fail-safe mode rf-filter high side switch lin vs 15 14 wkin 12 txd time-out timer slew rate control undervoltage reset sleep mode vcc switched off wake-up module atmel ata663431/ata663454 receiver v cc - + v cc window watchdog watchdog oscillator 11 cl15 7 wdosc 5 ntrig 6 mode v cc hsout 9 hsin 8 hv input (negative edge) hv input (positive edge) 10 lh v cc
3 ata663431/ata66 3454 [datasheet] 9232h?auto?09/14 2. pin configuration figure 2-1. pinning dfn16 table 2-1. pin description pin symbol function 1 rxd receive data output 2 en enable normal mode if the input is high 3 nres vcc undervoltage output, open drain, low at reset 4 txd transmit data input 5 ntrig low-level watchdog trigger input from micr ocontroller; if not n eeded, connect to vcc 6 mode control input for watchdog. low: watc hdog is on. high: watchdog is off 7 wdosc connection for external resistor to set the watchdog frequency 8 hsin high-side control input 9 hsout high-side switch output 10 lh failure output of the watchdog (limp home), open drain 11 cl15 ignition detection (edge sensitive); if not needed, connect to gnd 12 wkin high-voltage input for local wake-up reques t; if not needed, connect directly to vs 13 gnd ground 14 lin lin bus line input/output 15 vs supply voltage 16 vcc output voltage regulator 3.3v/5v/85ma backside heat slug, internally connected to gnd vcc atmel ata663431 ata663454 dfn16 3 x 5.5mm lin vs gnd rxd nres en txd wkin cl15 wdosc hsout mode lh ntrig hsin 116 89
ata663431/ata6634 54 [datasheet] 9232h?auto?09/14 4 3. pin description 3.1 supply pin (vs) lin operating voltage is v vs = 5v to 28v. in order to avoid false bus mess ages, undervoltage detection is implemented to disable transmission if v vs falls below v vs_th_n_f_down . after switching on v vs , the ic starts in fail-safe mode and the voltage regulator is switched on. the supply current in sleep mode is typically 10a and 47a in silent mode. 3.2 ground pin (gnd) the ic does not affect the lin bus in the event of gnd disconnection. it can handle gr ound shifts of up to 11.5% with respect to v vs . 3.3 voltage regulator output pin (vcc) the internal 3.3v/5v voltage regulator is capable of driving lo ads up to 85ma, supplying the microcontroller and other ics on the pcb, and is protected against overload by means of curr ent limitation and over temperature shutdown. furthermore, the output voltage is monitored and causes a reset signal at the nres output pin if it drops below a defined threshold v vcc_th_uv_down . 3.4 undervoltage reset output pin (nres) if the v vcc voltage falls below the undervoltage detection threshold v vcc_th_uv_down , nres switches to low after t res_f . even if v vcc = 0v, the nres stays low because it is internally driven from the vs voltage. if vs voltage ramps down, nres stays low until v vs < 1.5v and then becomes high-impedant. the undervoltage delay implemented keeps nres low for t reset = 4ms after v vcc reaches its nominal value. 3.5 bus pin (lin) a low-side driver is implemented with inte rnal current limitation and thermal shutdown as well as an internal pull-up resistor in compliance with lin specificat ion 2.x. the voltage range is from ?27v to +40v . this pin exhibits no reverse current from the lin bus to vs, even in the event of a gnd shift or supply disconnection. the lin receiver thresholds comply with the lin protocol specification. the fall time (transition from recessive to dominant state) and the rise time (transition from domi nant to recessive state) are slope-controlled. during a short-circuit at the lin pin to vbat the output limits the output current to i bus_lim . due to the power dissipation, the chip temperature exceeds t linoff and the lin output is switched off. the chip cools down and , after a hysteresis of t hys , switches the output on again. rxd stays on high because lin is high. during lin overtemperature switch-off, the vcc regulator works independently. during a short circuit from lin to gnd the ic can be switched into sleep or silent mode and even in this case the current consumption is lower than 100a in sleep mode and lower than 120a in silent mode. if the short circuit disappears, the ic starts with a remote wake-up. the reverse current is < 2a at pin lin during loss of v bat . this is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition.
5 ata663431/ata66 3454 [datasheet] 9232h?auto?09/14 3.6 bus data input/output (txd) in normal mode the txd pin is the microcontroller interface for controlling the state of the lin output. txd must be pulled to ground in order to drive the lin bus low. if txd is high or un connected (internal pull-up resist or), the lin output transistor is turned off and the bus is in the recessive state. if the txd pi n stays at gnd level while switch ing into normal mode, it must be pulled to high longer than 10s before the lin driver ca n be activated. this feature prevents the bus line from being driven unintentionally to dominant state after normal mode has b een activated (also in the case of a short circuit at txd to gnd). if txd is short-circuited to gnd, it is possib le to switch to sleep mode via the en pin after t > t dom . in fail-safe mode this pin is used as an output and signals the fail-safe source. an internal timer prevents the bus line from being driven perm anently in the dominant state. if txd is forced to low longer than t dom > 20ms, the lin bus driver is switch ed to the recessive state. nevertheless, when switching to sleep mode, the actual level at the txd pin is relevant. to reactivate the lin bus driver, txd needs to be set high for at least t dtorel (min 10s). 3.7 bus data output pin (rxd) in normal mode this pin reports the state of the lin bus to the microcontroller. lin high (recessive state) is indicated by a high level at rxd; lin low (dominant stat e) is indicated by a low level at rxd. the output is a push-pull stage switching between vcc and gnd. the ac characteristics are me asured with an external load capacitor of 20pf. in silent mode the rxd output switches to high. 3.8 enable input pin (en) the enable input pin controls the operating mode of the device. if en is high, the circuit is in normal mode, with the txd to lin and the lin to rxd the tr ansmission paths both active. the vcc voltage regulator operates with 3.3v/5v/85ma output capability. if en is switched to low while txd is st ill high, the device is forced into silent mode. no data transmission is possible and t he current consumption is reduced to i vssilent typ. 47a. the vcc regulator maintains full functionality. if en is switched to low while txd is low, the device is forced into sleep mode. this disables data transmission and the voltage regulator is switched off. pin en provides a pull-down resistor to force the tr ansceiver into recessive m ode if en is disconnected. 3.9 wake input pin (wkin) the wkin pin is a high-voltage input used for waking up the devic e from sleep mode or silent mode. it is usually connected to an external switch in the applicatio n to generate a local wake-up. a pull-up current source with typically 10a is implemented. the voltage threshold for a wake-up signal is typically 2v below v vs . if the wkin pin is not needed in the application, it can be connec ted directly to the vs pin. 3.10 cl15 pin the cl15 pin is a high-voltage input that can be used to wake up the device from sleep mode or silent mode. it is an edge- sensitive pin (low to-high transition). thus, even if the cl15 pin is at high voltage (v cl15 > v cl15h ), it is possible to switch the ic into sleep mode or silent mode. it is usually connected to the ignition for generating a local wake-up in the application if the ignition is switched on. the cl15 pin should be tied dire ctly to ground if not needed. a debounce timer with a value t dbcl15 of typically 100 s is implemented. to protect this pin a gainst transients, a serial resistor with 10k and a ceramic capacitor with 47nf are recommended. with this rc combination you can increase the cl15 wake-up time. 3.11 wdosc output pin the wdosc output pin provides a typical voltage of 1.23v inte nded to supply an external resistor with values between 34k and 120k . the value of the resistor adjusts the watchdog oscillat or frequency to provide a certain range of time windows. if the watchdog is disabled, the output voltage is switch ed off and the pin can either be tied to vcc or left open.
ata663431/ata6634 54 [datasheet] 9232h?auto?09/14 6 3.12 ntrig input pin the ntrig input pin is the trigger input for the window watchdog . a pull-up resistor is implemented. a falling edge triggers the watchdog. the trigger signal (low) must exceed a minimum time of t trigmin to generate a watchdog trigger and avoid false triggers caused by transients. 3.13 mode input pin (mode) connect the mode pin directly or via an external resistor to gnd for normal watc hdog operation. to debug the software of the connected microcontroller, connect t he mode pin to vcc and the watchdog is switched off. for fail-safe reasons, the mode pin has a self-holding function, pulling the input to gro und (i.e., watchdog enabled) in case of an open connection. note: if you do not use the watchdog, connect the mode pin directly to vcc. 3.14 limp home watchdog failure output (lh) the lh output pin indicates a failure of the watchdog. it is realized as a high-voltage open drain nmos structure. during power up or after a wake-up from sleep mode the lh output is switched off. as the watchdog is only working in normal and fail-safe mode, the state of th e lh output transistor can change only in th ese two modes. in silent mode the lh output remains in the same state as it wa s before switching into silent mode. if a watchdog reset occurs, the lh output transistor switches on immediately, and it switches off only after three correct consecutive watchdog trigger pulses have been occurred at the ntrig pin. 3.15 high-side switch pins (hsout, hsin) this high-side switch is designed for low-power loads such as leds, sensors or a voltage divider for measuring the supply voltage. it is functional in all operating modes of the chip ex cept for sleep mode. its structure is connected to the vs supply pin. this pin is short-circuit protected and also protecte d against overheating, whereas the protective shutdown is debounced and latched. in other word s, after a protective shutdown of the output switch, th e control line hsin has to go to low level first before the out put can be restarted again. the high-side switch is controlled via the low-voltage input pin hsin. if the input is high, the output is switched on. for fai l- safe reasons, the hsin input is equipped with a pull-down resistor to gnd. this keeps the high-side switch off in case of a missing connection from the controller. please note that in case of a disconnec ted system ground, the module can be suppl ied via the connect ed load on the high- side output and an internal esd structure. this is the case if the load has a different groun d connection than the pcb. see also the ?absolute maximum ratings? se ction for current limits in such cases.
7 ata663431/ata66 3454 [datasheet] 9232h?auto?09/14 4. functional description 4.1 physical layer compatibility because the lin physical layer is independent of higher lin layers (such as the li n protocol layer), all nodes with a lin physical layer according to revision 2.x can be mixed with lin ph ysical layer nodes found in older versions (i.e., lin 1.0, lin 1.1, lin 1.2, lin 1.3) without any restrictions. 4.2 operating modes figure 4-1. operating modes a: vs > v vs_th_u_f_up (2.4v) b: vs < v vs_th_u_down (1.9v) c: bus wake-up event (lin) e: vs < v vs_th_n_f_down (3.9v) f: vs > v vs_th_f_n_up (4.9v) d: vcc < v vcc_th_uv_down (2.4v/4.2v) or wd-reset en = 1 en = 0 go to sleep command go to silent command en = 0 txd = 0 b c & f g & f en = 0 txd = 0 en = 0 txd = 1 en = 1 & f txd = 1 d, e b a b & f fail-safe mode vcc: on vcc monitor active communication: off wake-up signaling undervoltage signaling watchdog: on normal mode vcc: on vcc monitor active communication: on watchdog: on sleep mode vcc: off communication: off watchdog: off unpowered mode all circuitry off silent mode vcc: on vcc monitor active communication: off watchdog: off c & f, g & f, d en = 1 & f & f & d & f g: local wake-up event (wkin or cl15) table 4-1. operating modes (mode pin is always low) operating modes transceiver voltage regulator watchdog lh high-side output lin txd rxd fail-safe off on on wd dependent hsin-dependent recessive signaling fail-safe sources (see table 4-2 ) normal on on on wd dependent hsin-dependent txd dependent follows data transmission silent off on off remains in previous state hsin-dependent recessive high high sleep/unpowered off off off off off recessive low low
ata663431/ata6634 54 [datasheet] 9232h?auto?09/14 8 4.2.1 normal mode this is the normal transmission and receiving mode of the lin interface. the vcc voltage regulator works with 3.3v/5v output voltage. the watchdog needs a trigger signal from ntrig to avoid resets at nres. if nres switches to low, the ic changes its state to fail-safe mode. 4.2.2 silent mode a falling edge at en while txd is high switches the ic into si lent mode. the txd signal has to be logic high during the mode select window. the transmission path is disabled in silent mode . the voltage regulator is active. the overall supply current from vbat is a combination of the i vssilent of typ. 47a plus the vcc regulator output current i vcc . figure 4-2. switching to silent mode in silent mode, the internal slave termination between the lin pi n and vs pin is disabled to minimize current consumption in case the lin pin is short-circuited to g nd. only a weak pull-up current (typically 10a) is present between the lin pin and the vs pin. silent mode can be activated regardless of the current level on the lin pin or wkin pin. if an undervoltage condition occurs, nres is switched to lo w and the atmel ata663431/ata 663454 changes its state to fail-safe mode. delay time silent mode t d_silent = maximum 20s mode select window lin switches directly to recessive mode t d = 3.2s lin vcc nres txd en normal mode silent mode
9 ata663431/ata66 3454 [datasheet] 9232h?auto?09/14 4.2.3 sleep mode a falling edge at en while txd is low switches the ic to sleep mode. the txd signal has to be logic low during the mode select window. figure 4-3. switching to sleep mode in order to avoid any influence on the lin pin while switching into sleep mode, it is possible to switch the en to low up to 3.2s earlier than the txd. the best and easiest way is to generate two simultaneous falling edges at txd and en. the transmission path is disabl ed in sleep mode. supply current from vbat is typically i vssleep = 10a. the vcc regulator is switched off; nres and rxd are low. the internal slave terminat ion between the lin and vs pins is disabled to minimize current consumption in case the lin pin is short-circuited to gnd. only a weak pu ll-up current (typically 10a) between the lin pin and vs pin is present. sleep mode can be activated inde pendently from the current leve l on the lin pin. a voltage less than the lin pre-wake detection v linl at the lin pin activates th e internal lin receiver and starts the wake-up detection timer. if txd is short-circuited to g nd, it is possible to switch to sleep mode via en after t > t dom . delay time sleep mode t d_sleep = maximum 20s lin switches directly to recessive mode t d = 3.2s lin vcc nres txd en sleep mode normal mode mode select window
ata663431/ata6634 54 [datasheet] 9232h?auto?09/14 10 4.2.4 fail-safe mode the device automatically switches to fail-safe mode at system power-up. the voltage regulator and the watchdog are switched on. the nres output remains low for t res = 4ms and resets the microcontroller. lin communication is switched off. the ic stays in this mode until en is switched to high. the ic then changes to normal mode. a low at nres switches the ic directly into fail-safe mode. during fail-safe mode the txd pi n is an output and together with the rxd output pin transmits a signal indicating the fail-safe source. if the device enters fail-safe mode comi ng from normal mode (en=1) due to a v vs undervoltage condition (v vs 11 ata663431/ata66 3454 [datasheet] 9232h?auto?09/14 4.3 wake-up scenarios from silent mode or sleep mode 4.3.1 remote wake-up via lin bus 4.3.1.1 remote wake-up from silent mode a remote wake-up from silent mode is only possible if tx d is high. a voltage less than the lin pre-wake detection v linl at the lin pin activates the internal lin receiver and starts the wake-up detection timer. a falling edge at the lin pin followed by a dominant bus level maintained for a given time period (> t bus ) and the following rising edge at the lin pin (see figure 4-4 ) result in a remote wake-up request. the device switches from silent mode to fail-safe mode, the vcc voltage regulator remains activated and the internal lin slave termination resistor is switched on. the remote wake-up request is indicated by a low level at the rxd and txd pins (strong pull-down at txd). en high can be used to switch directly to normal mode. figure 4-4. lin wake-up from silent mode low fail-safe mode normal mode en high high nres en vcc rxd lin bus bus wake-up filtering time t bus high txd high watchdog watchdog off start watchdog lead time t d low (strong pull-down)
ata663431/ata6634 54 [datasheet] 9232h?auto?09/14 12 4.3.1.2 remote wake-up from sleep mode a voltage less than the lin pre-wake detection v linl at the lin pin activates the internal lin receiver and starts the wake-up detection timer. a falling edge at the lin pin followed by a dominant bus level maintained for a given time period (> t bus ) and a subsequent rising edge at the lin pin results in a remote wake-up req uest. the device switches from sleep mode to fail-safe mode. the vcc regulator is activated, and the internal lin slave term ination resistor is switched on. the remote wake-up request is indicated by a low level at rxd and txd (strong pull-down at txd). en high can be used to switch directly from sleep/sil ent to fail-safe mode. if en is still high after v cc ramp-up and the undervoltage reset time, the ic switches to normal mode. figure 4-5. lin wake-up from sleep mode t vcc off state on state low fail-safe mode normal mode en high microcontroller start-up time delay reset time low (strong pull-down) low nres en vcc rxd lin bus bus wake-up filtering time t bus high txd high high watchdog off watchdog start watchdog lead time t d
13 ata663431/ata66 3454 [datasheet] 9232h?auto?09/14 4.3.2 local wake-up via wkin pin a falling edge at the wkin pin followed by a low level maintained for a given time period (> t wkin ) results in a local wake-up request. the device switches to fail-saf e mode. the internal slave termination resistor is switched on. the local wake-up request is indicated by a low level at t he txd pin to generate an interrupt for the microcontroller. when the wkin pin is low, it is possible to switch to silent mode or sleep mode via the en pin. in this case, the wake-up signal has to be switched to high > 10s before the negative edge at wkin starts a new local wake-up request. figure 4-6. local wake-up via wkin pin from sleep mode t vcc off state on state high fail-safe mode normal mode en high microcontroller start-up time delay reset time low (strong pull-down) low nres en vcc rxd wkin txd wake filtering time t wkin state change watchdog off watchdog start watchdog lead time t d
ata663431/ata6634 54 [datasheet] 9232h?auto?09/14 14 figure 4-7. local wake-up via wkin pin from silent mode 4.3.3 local wake-up via cl15 a voltage on pin cl15 above v cl15h for at least t dbcl15 results in a local wake-up request. the device switches to fail-safe mode. the internal slave termination resistor is switched on. the local wake-up reques t is indicated by a low level at the txd pin to generate an interrupt for the microcontroller. even when th e cl15 pin is high, it is possible to switch to silent mode o r sleep mode via the en pin. in this case, the wake-up signal at cl15 has to be switched to low > 10s before the rising edge at cl15 starts a new local wake-up request. 4.3.4 wake-up source recognition the device can distinguish between different wake-up sources (see table 4-3 ). the wake-up source can be read on the txd and rxd pin in fail-safe mode. these flags are immediately reset if the microcontroller sets the en pin to high and the ic is in normal mode. fail-safe mode normal mode en high high nres en vcc rxd wkin txd low (strong pull-down) wake filtering time t wkin state change watchdog off watchdog start watchdog lead time t d table 4-3. signaling in fail-safe mode fail-safe sources txd rxd lin wake-up (lin pin) low low local wake-up (wkin pin or cl15 pin) low high v vs_th_n_f_down (battery) undervoltage detection (v vs <3.9v) high low
15 ata663431/ata66 3454 [datasheet] 9232h?auto?09/14 4.4 behavior under low supply voltage conditions after the battery voltage has been connected to the application circuit, the voltage at the vs pin increases according to the block capacitor (see figure 4-12 on page 17 ). if v vs is higher than the minimum v vs operation threshold v vs_th_u_f_up (typ. 2.25v), the ic mode changes from unpowered mode to fail-safe mode. as soon as v vs exceeds the undervoltage threshold v vs_th_f_n_up (typ. 4.6v), the lin transceiver can be activated. th e vcc output voltage reaches its nominal value after t vcc . this parameter depends on the externally applied vcc capacito r and the load. the nres output is low for the reset time delay t reset . no mode change is possible during this time t reset . the behavior of vcc, nres and vs is shown in following diagrams (ramp-up and ramp-down): figure 4-8. vcc and nres versus vs (ramp-up) for ata663431 figure 4-9. vcc and nres versus vs (ramp-down) for ata663431 v (v) vs (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 vs vcc nres v (v) vs (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 vs vcc nres
ata663431/ata6634 54 [datasheet] 9232h?auto?09/14 16 figure 4-10. vcc and nres versus vs (ramp-up) for ata663454 figure 4-11. vcc and nres versus vs (ramp-down) for ata663454 please note that the upper graphs are only valid if the v vs ramp-up and ramp-down time is much slower than the vcc ramp- up time t vcc and the nres delay time t reset . if during sleep mode the voltage level of v vs drops below the undervoltage detection threshold v vs_th_n_f_down (typ. 4.3v), the operating mode is not changed and no wake-up is possible. only if the supply voltage on pin vs drops below the v vs operation threshold v vs_th_u_down (typ. 2.05v) does the ic switch to unpowered mode. if during silent mode the vcc voltage drops below the vcc undervoltage threshold v vcc_th_uv_down the ic switches into fail- safe mode. if the supply voltage on pin vs drops below the v vs operation threshold v vs_th_u_down (typ. 2.05v), does the ic switch to unpowered mode. if during normal mode the voltage level on pin vs drops below the v vs undervoltage detection threshold v vs_th_n_f_down (typ. 4.3v), the ic switches to fail-safe mode. this means the lin tr ansceiver is disabled in order to avoid malfunctions or false bus messages. the voltage regulator remains active. for ata663431 : in this undervoltage situation, it is possible to switch the device into sleep mode or silent mode through a falling edge at the en input pin. this feature ensures that it is always possible to switch to these two current saving modes so that current cons umption can be reduced even further. when the vcc voltage drops below the vcc undervoltage threshold v vcc_th_uv_down (typ. 2.6v) the ic switches into fail-safe mode. for ata663454 : because of the vcc undervoltage condition in this situation, the ic is in fail-safe mode and can be switched into sleep mode only. only when the supply voltage v vs drops below the operation threshold v vs_th_u_down (typ. 2.05v) does the ic switch into unpowered mode. the current consumption of the ata663431/ata663454 in sil ent mode is always below 200a, even when the supply voltage v vs is lower than the regulator?s nominal output voltage vcc. v (v) vs (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 vs nres vcc v (v) vs (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 vs nres vcc
17 ata663431/ata66 3454 [datasheet] 9232h?auto?09/14 4.5 voltage regulator figure 4-12. vcc voltage regulator: supply voltage ramp-up and ramp-down the voltage regulator needs an external capacitor for compensation and to smooth t he disturbances from the microcontroller. it is recommended to use a mlc capacitor with a minimum capacitance of 1.8f together with a 100nf ceramic capacitor. depending on the application, the values of these capacitors can be modified by the customer. when the atmel ata663431/ata663454 is being soldered onto th e pcb, it is mandatory to c onnect the heat slug with a wide gnd plate on the printed board to achieve a good heat sink. the main power dissipation of the ic is created from the vcc regulator output current i vcc , which is needed for the application. figure 4-13 shows the safe operating area of the atmel at a663431/ata663454 without considering any output current of the high-side output hsout. figure 4-13. power dissipation: safe oper ating area: regulator?s output current i vcc versus supply voltage v vs at different ambient temperatures (r thja = 45k/w assumed) vs v 12v 5.0v/3.3v 4.8v/2.9v 5.0v/3.3v t vcc t vcc t reset 2.4v t res_f nres t v vs_th_n_f_down v vs [v] i_vcc [ma] tamb = 125c tamb = 115c tamb = 105c tamb = 95c tamb = 85c 0 10 20 30 40 50 60 70 80 90 5 6 7 8 9 1011121314 15161718
ata663431/ata6634 54 [datasheet] 9232h?auto?09/14 18 4.6 watchdog the watchdog anticipates a trigger signal from the microcon troller at the ntrig (negative edge) input within a time window of t wd . the trigger signal must exceed a minimum time of t trigmin > 200ns. if a trigger signal is not received, a reset signal is generated at output nres and the lh output transistor switches on. the timing basis of the watchdog is provided by the internal oscillator. its time period, t osc , is adjustable via the external resistor r wdosc (34k to 120k ). during silent or sleep mode the watchdog is switched off to reduce current consumption. the minimum time for the first watchdog pulse is required after the undervoltage reset at nres disa ppears, it is defined as lead time t d . after wake-up from sleep mode, the lead time t d starts with the rising edge at the nres output. af ter a wake-up from silent mode, the lead time t d starts with the falling edge at the txd pin. the limp home output lh is a high voltage nmos open drain structure which is signaling watchdog failures. it works independently of the vcc voltage. so it is possible to switch on some external devices in the case of a watchdog failure independent from the microcontroller and the vcc voltage. during power up or after a wake-up from sleep mode the lh output is switched off. if a watchdog reset occurs, the lh output transistor switches on immediately, and it switches off only after three correct consecutive watchdog trigger pulses have been occurred at the ntrig pin. as the watchdog is only working in normal and fail-safe mode, the state of the lh output trans istor can change only in these two modes. in silent mode the lh output remains in the same state as it was before switching into silent mode. when the watchdog is disabled via a high level at the mode pin or duri ng sleep or unpowered mode, the lh output is also disabled. the behavior of the lh output when the watchdog is ac tive during fail-safe and normal mode is depicted in figure 4-14 . figure 4-14. limp home (lh) state diagram in sleep mode and unpowered mode the wa tchdog and therefore the lh output are deactivated. in silent mode the lh output remains in the same state as it wa s before switching into silent mode lh set active state 3 0 1 lh off state lh set active state 2 lh set active state state 0: lh output is switched off state 1: lh output is switched on state 2: lh output is switched on state 3: lh output is switched on wd_reset power-up or wake-up from sleep mode 3rd trigger 1st trigger 2nd trigger wd_reset wd_reset
19 ata663431/ata66 3454 [datasheet] 9232h?auto?09/14 4.6.1 typical timing sequence with r wdosc = 51k the trigger signal t wd is adjustable between 20ms and 64ms using the external resistor r wdosc . for example, with an ex ternal resistor of r wdosc = 51k 1%, the typical parameters of the watchdog are as follows: t osc = (0.405 r wdosc ? 0.0004 (r wdosc ) 2 ) 2 (r wdosc in k ; t osc in s) t osc = 39.3 s due to 51k t d = 3984 39.2 s = 154.8ms t 1 = 527 39.2 s = 20.6ms t 2 = 553 39.3 s = 21.6ms t nres = constant = 4ms after ramping up the battery voltage, the 5v regulator is switched on. the reset output nr es stays low for the time t reset (typically 4ms), then it swit ches to high and the watchdog waits for the tr igger sequence from the microcontroller. during power up or after a wake-up from sleep mode the lh output is switched off. if a watchdog reset occurs, the lh output transistor switches on immediately, and it switches off only after three correct consecutive watchdog trigger pulses have been occurred at the ntrig pin. the lead time, t d , follows the reset and is t d = 155ms. in this time, the first watchdog pulse from the microcontroller is requir ed. if the trigger pulse ntrig occurs during this time, the time t 1 starts immediately. if no trigger signal occurs during the time t d , a watchdog reset with t nres = 4ms will reset the microcontroller after t d = 155ms and the lh output transistor switches on. the times t 1 and t 2 have a fixed relationship. a trigger signal from the microcontroller is anticipated within the time frame of t 2 = 21.6ms. to avoid false triggering from glit ches, the trigger pulse must be longer than t trigmin > 200ns. this slope serves to restart the watchdog seq uence. if the triggering signal fails in this open window t 2 , the nres output is drawn to ground as well as the lh output. a trigger signal during the closed window t 1 immediately switches nres and lh to low. figure 4-15. timing sequence with r wdosc = 51k t nres = 4ms undervoltage reset watchdog reset t reset = 4ms t trig > 200ns t 1 = 20.6ms t 2 = 21ms t 2 t 1 t wd t d = 155ms vcc 3.3v/5v ntrig nres t 1 t 2 lh lh output transistor off lh output transistor on
ata663431/ata6634 54 [datasheet] 9232h?auto?09/14 20 4.6.2 worst-case calculation with r wdosc = 51k the internal oscillator has a tole rance of 20%. this means that t 1 and t 2 can also vary by 20%. the worst-case calculation for the watchdog period t wd is calculated as follows. the ideal watchdog time t wd is between the maximum t 1 and the minimum t 1 plus the minimum t 2 . t 1,min = 0.8 t 1 = 16.5ms, t 1,max = 1.2 t 1 = 24.8ms t 2,min = 0.8 t2 = 17.3ms, t 2,max = 1.2 t 2 = 26ms t wdmax = t 1,min + t 2,min = 16.5ms + 17.3ms = 33.8ms t wdmin = t 1,max = 24.8ms t wd = 29.3ms 4.5ms (15%) a microcontroller with an oscillator tolerance of 15% is sufficient to supply the trigger inputs correctly. if the wdosc pin has a short circuit to gnd or the exte rnal resistor at the wdosc pin is disconnected, the watchdog runs with an internal oscillator and guarantees a reset and activation of the lh output. table 4-4. typical watchdog timings r wdosc k oscillator period t osc /s lead time t d /ms closed window t 1 /ms open window t 2 /ms trigger period from microcontroller t wd /ms reset time t nres /ms 34 13.3 2 105 14.0 14.7 19.9 4 51 19.61 2 154.8 20.64 21.67 29.32 4 91 3.54 2 264.80 35.32 37.06 50.14 4 120 42.84 2 338.22 45.11 47.34 64.05 4
21 ata663431/ata66 3454 [datasheet] 9232h?auto?09/14 5. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters symbol min. typ. max. unit supply voltage v vs - dc voltage - t a = 25c, t pulse 500ms, i vcc 85ma - t a = 25c, t pulse 2min, i vcc 85ma v vs ?0.3 +40 +43.5 +28 v logic pin voltage levels (txd, rxd, en, hsin, mode, wdosc, nres, ntrig) v logic ?0.3 +5.5 v logic pin output dc currents i logic ?5 +5 ma lin bus levels v lin - dc voltage - pulse time 500ms v lin ?27 +40 +43.5 v v v cc - dc voltage - dc input current v vcc i vcc ?0.3 +5.5 +200 v ma logic level pins injection currents - dc currents - t pulse 2min i logic ?5 ?5 0.1 +5 ma lh voltage levels v lh ?0.3 v vs + 0.3 v hsout - dc voltage - dc output current - dc current injection levels v hsout < 0v and v hsout > v vs v hsout i hsout i hsout ?0.3 ?50 ?20 v vs + 0.3 +10 v ma ma cl15 voltage levels - dc voltage v cl15 ?0.3 +40 v wkin voltage levels - dc voltage -transient voltage according to iso7637 (coupling 1nf), (with 2.7k serial resistor) v wkin ?0.3 ?150 +40 +100 v esd according to ibee lin emc test spec. 1.0 following iec 61000-4-2 - pin vs, wkin and lin to gnd (cl15 and wkin with ext. circuitry according to applications diagram) 6 kv esd according to iso10605, with 330pf/330 - pin hsout (100 series resistor, 22nf to gnd) to gnd 6 kv esd (hbm following stm5.1 with 1.5k /100pf) - pin vs, lin, wkin, hsout, cl15 to gnd 6 kv component level esd (hbm according to ansi/esd stm5.1) jesd22-a114 aec-q100 (002) 3 kv cdm esd stm 5.3.1 750 v esd machine model aec-q100-revf(003) 100 v junction temperature t j ?40 +150 c storage temperature t s ?55 +150 c
ata663431/ata6634 54 [datasheet] 9232h?auto?09/14 22 6. thermal characteristics parameters symbol min. typ. max. unit thermal resistance junction to heat slug r thjc 8 k/w thermal resistance junction to ambient, where heat slug is soldered to pcb according to jedec r thja 45 k/w thermal shutdown of v vcc regulator t vccoff 150 165 180 c thermal shutdown of lin output t linoff 150 165 180 c thermal shutdown of high-side driver t dsoff 150 165 180 c thermal shutdown hysteresis t hys 10 c 7. electrical characteristics 5v < v vs < 28v, ?40c < t j < 150c; unless otherwise specified all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* 1 vs pin 1.1 nominal dc voltage range vs v vs 5 13.5 28 v a 1.2 supply current in sleep mode sleep mode v lin > v vs ? 0.5v v vs < 14v, t = 27c vs i vssleep 5 10 15 a b sleep mode v lin > v vs ? 0.5v v vs < 14v vs i vssleep 3 11 18 a a sleep mode, v lin = 0v bus shorted to gnd v vs < 14v vs i vssleep_short 20 50 100 a a 1.3 supply current in silent mode bus recessive 5.5v < v vs < 14v, hs-driver off without load at vcc t = 27c vs i vssilent 30 47 58 a b bus recessive 5.5v < v vs < 14v, hs-driver off without load at vcc vs i vssilent 30 50 64 a a bus recessive v vs < 5.5v, v vcc > v vcc_th_uv hs-driver off without load at vcc vs i vssilent 30 150 190 a a silent mode 5.5v < v vs < 14v, hs-driver off without load at vcc bus shorted to gnd vs i vssilent_short 50 90 130 a a 1.4 supply current in normal mode bus recessive v vs < 14v, hs-driver off without load at vcc, watchdog on, 51k at wdosc vs i vsrec 300 400 500 a a bus recessive v vs < 14v, hs-driver off without load at vcc, watchdog off (v mode = v vcc ) vs i vsrec 150 250 350 a a *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
23 ata663431/ata66 3454 [datasheet] 9232h?auto?09/14 1.5 supply current in normal mode bus dominant (internal lin pull-up resistor active) v vs < 14v, hs-driver off without load at vcc, watchdog on, 51k at wdosc vs i vsdom 600 900 1150 a a bus dominant (internal lin pull-up resistor active) v vs < 14v, hs-driver off without load at vcc, watchdog off (v mode = v vcc ) vs i vsdom 500 750 1000 a a 1.6 supply current in fail-safe mode bus recessive 5.5v < v vs < 14v, hs-driver off without load at vcc, watchdog on, 51k at wdosc vs i vsfail 100 200 300 a a bus recessive 5.5v < v vs < 14v, hs-driver off without load at vcc, watchdog off (v mode = v vcc ) vs i vsfail 40 70 100 a a bus recessive 2v < v vs < 5.5v, hs-driver off without load at vcc watchdog on, 51k at wdosc vs i vsfail 150 280 320 a a bus recessive 2v < v vs < 5.5v, hs-driver off without load at vcc watchdog off (v mode = v vcc ) vs i vsfail 50 150 200 a a 1.7 vs undervoltage threshold (switching from normal mode to fail-safe mode) decreasing supply voltage vs v vs_th_n_f_dow n 3.9 4.3 4.7 v a increasing supply voltage vs v vs_th_f_n_up 4.1 4.6 4.9 v a 1.8 vs undervoltage hysteresis vs v vs_hys_f_n 0.1 0.25 0.4 v a 1.9 vs operation threshold (switching to unpowered mode) switch to unpowered mode vs v vs_th_u_down 1.9 2.05 2.3 v a switch from unpowered mode to fail-safe mode vs v vs_th_u_f_up 2.0 2.25 2.4 v a 1.10 vs undervoltage hysteresis vs v vs_hys_u 0.1 0.2 0.3 v a 2 rxd output pin 2.1 low-level output sink capability normal mode, v lin =0v, i rxd =2ma rxd v rxdl 0.2 0.4 v a 2.2 high-level output source capability normal mode v lin =v s , i rxd = ?2ma rxd v rxdh v cc ? 0.4v v cc ? 0.2v v a 3 txd input/output pin 3.1 low-level voltage input txd v txdl ?0.3 +0.8 v a 3.2 high-level voltage input txd v txdh 2 v cc + 0.3v v a 3.3 pull-up resistor v txd =0v txd r txd 40 70 100 k a 3.4 high-level leakage current v txd =v cc txd i txd ?3 +3 a a 7. electrical characteristics (continued) 5v < v vs < 28v, ?40c < t j < 150c; unless otherwise specified all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
ata663431/ata6634 54 [datasheet] 9232h?auto?09/14 24 3.5 low-level output sink current at wake-up request fail-safe mode v lin = v vs v wkin = 0v v txd = 0.4v txd i txd 2 2.5 8 ma a 4 en input pin 4.1 low-level voltage input en v enl ?0.3 +0.8 v a 4.2 high-level voltage input en v enh 2 v cc + 0.3v v a 4.3 pull-down resistor v en = v vcc en r en 50 125 200 k a 4.4 low-level input current v en = 0v en i en ?3 +3 a a 5 nres open drain output pin 5.1 low-level output voltage v vs 5.5v i nres =2ma nres v nresl 0.2 0.4 v a 5.2 undervoltage reset time v vs 5.5v c nres = 20pf nres t reset 2 4 6 ms a 5.3 reset debounce time for falling edge v vs 5.5v c nres = 20pf nres t res_f 0.5 10 s a 5.4 switch-off leakage current v nres =5.5v nres i nres_l ?3 +3 a a 6 vcc voltage regulator ata663431 6.1 output voltage vcc 4v < v vs < 18v (0ma to 50ma) vcc v vccnor 3.234 3.366 v a 4.5v < v vs < 18v (0ma to 85ma) vcc v vccnor 3.234 3.366 v c 6.2 output voltage v vcc at low v vs 3v < v vs < 4v vcc v vcclow v vs ? v d 3.366 v a 6.3 regulator drop voltage v vs > 3v, i vcc = ?15ma vcc v d1 200 250 mv a 6.4 regulator drop voltage v vs > 3v, i vcc = ?50ma vcc v d2 300 500 mv a 6.5 line regulation maximum 4v < v vs < 18v vcc vcc line 0.1 0.2 % a 6.6 load regulation maximum 5ma < i vcc < 50ma vcc vcc load 0.1 0.5 % a 6.7 output current limitation v vs > 4v vcc i vcclim ?180 ?120 ma a 6.8 load capacity mlc capacitor vcc c load 1.8 2.2 f d 6.9 vcc undervoltage threshold (nres on) referred to vcc v vs > 4v vcc v vcc_th_uv_dow n 2.4 2.6 2.8 v a vcc undervoltage threshold (nres off) referred to vcc v vs > 4v vcc v vcc_th_uv_up 2.5 2.7 2.9 v a 6.10 hysteresis of vcc undervoltage threshold referred to vcc v vs > 4v vcc v vcc_hys_uv 100 200 300 mv a 6.11 ramp-up time v vs > 4v to vcc = 3.3v c vcc = 2.2f i load = ?5ma at vcc vcc t vcc 1 1.5 ms a 7. electrical characteristics (continued) 5v < v vs < 28v, ?40c < t j < 150c; unless otherwise specified all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
25 ata663431/ata66 3454 [datasheet] 9232h?auto?09/14 7 vcc voltage regulator ata663454 7.1 output voltage vcc 5.5v < v vs < 18v (0ma to 50ma) vcc v vccnor 4.9 5.1 v a 6v < v vs < 18v (0ma to 85ma) vcc v vccnor 4.9 5.1 v c 7.2 output voltage v cc at low v vs 4v < v vs < 5.5v vcc v vcclow v vs ? v d 5.1 v a 7.3 regulator drop voltage v vs > 4v, i vcc = ?20ma vcc v d1 100 200 mv a 7.4 regulator drop voltage v vs > 4v, i vcc = ?50ma vcc v d2 300 500 mv a 7.5 regulator drop voltage v vs > 3.3v, i vcc = ?15ma vcc v d3 150 mv a 7.6 line regulation maximum 5.5v < v vs < 18v vcc vcc line 0.1 0.2 % a 7.7 load regulation maximum 5ma < i vcc < 50ma vcc vcc load 0.1 0.5 % a 7.8 output current limitation v vs > 5.5v vcc i vcclim ?180 ?120 ma a 7.9 load capacity mlc capacitor vcc c load 1.8 2.2 f d 7.10 vcc undervoltage threshold (nres on) referred to vcc v vs > 4v vcc v vcc_th_uv_dow n 4.2 4.4 4.6 v a vcc undervoltage threshold (nres off) referred to vcc v vs > 4v vcc v vcc_th_uv_up 4.3 4.6 4.8 v a 7.11 hysteresis of undervoltage threshold referred to vcc v vs > 5.5v vcc v vcc_hys_uv 100 200 300 mv a 7.12 ramp-up time v vs > 5.5v to vcc = 5v c vcc = 2.2f i load = ?5ma at vcc vcc t vcc 1 1.5 ms a 8 lin bus driver: bus load conditions: load 1 (small): 1nf, 1k ; load 2 (large): 10nf, 500 ; c rxd = 20pf, load 3 (medium): 6.8nf, 660 characterized on samples 10.7 and 10.8 specifies the timing parameters for proper o peration at 20kb/s and 10.9kb /s and 10.10kb/s at 10.4kb/s 8.1 driver recessive output voltage load1/load2 lin v busrec 0.9 v vs v vs v a 8.2 driver-dominant voltage v vs = 7v r load = 500 lin v _losup 1.2 v a 8.3 driver-dominant voltage v vs = 18v r load = 500 lin v _hisup 2 v a 8.4 driver-dominant voltage v vs = 7v r load = 1000 lin v _losup_1k 0.6 v a 8.5 driver-dominant voltage v vs = 18v r load = 1000 lin v _hisup_1k 0.8 v a 8.6 pull-up resistor to v vs the serial diode is mandatory lin r lin 20 30 47 k a 8.7 voltage drop at the serial diodes in pull-up path with r slave i serdiode = 10ma lin v serdiode 0.4 1.0 v d 8.8 lin current limitation v bus = v bat_max lin i bus_lim 40 120 200 ma a 8.9 input leakage current at the receiver including pull-up resistor as specified input leakage current driver off v bus = 0v v vs = 12v lin i bus_pas_dom ?1 ?0.35 ma a 7. electrical characteristics (continued) 5v < v vs < 28v, ?40c < t j < 150c; unless otherwise specified all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
ata663431/ata6634 54 [datasheet] 9232h?auto?09/14 26 8.10 leakage current lin recessive driver off 8v < v vs < 18v 8v < v bus < 18v v bus v bat lin i bus_pas_rec 10 20 a a 8.11 leakage current when control unit disconnected from ground. loss of local ground must not affect communication in the residual network gnd device = v vs v vs = 12v 0v < v bus < 18v lin i bus_no_gnd ?10 +0.5 +10 a a 8.12 leakage current at disconnected battery. node has to sustain the current that can flow under this condition. bus must remain operational under this condition. v vs disconnected v sup_device = gnd 0v < v bus < 18v lin i bus_no_bat 0.1 2 a a 8.13 capacitance on the lin pin to gnd lin c lin 20 pf d 9 lin bus receiver 9.1 center of receiver threshold v bus_cnt = (v th_dom + v th _ rec )/2 lin v bus_cnt 0.475 v vs 0.5 v vs 0.525 v vs v a 9.2 receiver dominant state v en = 5v/3.3v lin v busdom ?27 0.4 v vs v a 9.3 receiver recessive state v en = 5v/3.3v lin v busrec 0.6 v vs 40 v a 9.4 receiver input hysteresis v hys = v th_rec ? v th_dom lin v bushys 0.028 v vs 0.1 v vs 0.175 v vs v a 9.5 pre-wake detection lin high-level input voltage lin v linh v vs ? 2v v vs + 0.3v v a 9.6 pre-wake detection lin low-level input voltage activates the lin receiver lin v linl ?27 v vs ? 3.3v v a 10 internal timers 10.1 dominant time for wake-up via lin bus v lin = 0v lin t bus 50 100 150 s a 10.2 time delay for mode change from fail-safe mode to normal mode via the en pin v en = 5v/3.3v en t norm 5 15 20 s a 10.3 time delay for mode change from normal mode to sleep mode via the en pin v en = 0v en t sleep 5 15 20 s a 10.4 txd-dominant time-out time v txd = 0v txd t dom 20 40 60 ms a 10.6 time delay for mode change from silent mode to normal mode via the en pin v en = 5v/3.3v en t s_n 5 15 40 s a 10.7 duty cycle 1 th rec(max) = 0.744 v vs th dom(max) = 0.581 v vs v vs = 7.0v to 18v t bit = 50s d1 = t bus_rec(min) /(2 t bit ) lin d1 0.396 a 7. electrical characteristics (continued) 5v < v vs < 28v, ?40c < t j < 150c; unless otherwise specified all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
27 ata663431/ata66 3454 [datasheet] 9232h?auto?09/14 10.8 duty cycle 2 th rec(min) = 0.422 v vs th dom(min) = 0.284 v vs v vs = 7.6v to 18v t bit = 50s d2 = t bus_rec(max) /(2 t bit ) lin d2 0.581 a 10.9 duty cycle 3 th rec(max) = 0.778 v vs th dom(max) = 0.616 v vs v vs = 7.0v to 18v t bit = 96s d3 = t bus_rec(min) /(2 t bit ) lin d3 0.417 a 10.10 duty cycle 4 th rec(min) = 0.389 v vs th dom(min) = 0.251 v vs v vs = 7.6v to 18v t bit = 96s d4 = t bus_rec(max) /(2 t bit ) lin d4 0.590 a 10.11 slope time falling and rising edge at lin v vs = 7.0v to 18v lin t slope_fall t slope_rise 3.5 22.5 s a 10.12 txd release time after dominant time-out detection txd t dtorel 10 20 s b 11 receiver electrical ac parameters of the lin physical layer lin receiver, rxd load conditions: c rxd = 20pf 11.1 propagation delay of receiver v vs = 7.0v to 18v t rx_pd = max(t rx_pdr , t rx_pdf ) rxd t rx_pd 6 s a 11.2 symmetry of receiver propagation delay rising edge minus falling edge v vs = 7.0v to 18v t rx_sym = t rx_pdr ? t rx_pdf rxd t rx_sym ?2 +2 s a 12 wkin pin 12.1 high-level input voltage wkin v wkinh v vs ? 1v v vs + 0.3v v a 12.2 low-level input voltage initializes a wake-up signal wkin v wkinl ?1 v vs ? 3.3v v a 12.3 wkin pull-up current v vs < 28v, v wkin = 0v wkin i wkin ?30 ?10 a a 12.4 high-level leakage current v vs = 28v, v wkin = 28v wkin i wkinl ?5 +5 a a 12.5 debounce time of low pulse for wake-up via wkin pin v wkin = 0v wkin t wkin 50 100 150 s a 13 watchdog oscillator 13.1 voltage at wdosc in normal or fail-safe mode i wd_osc = ?200 a v vs 4v wdosc v wdosc 1.13 1.23 1.33 v a 13.2 possible values of resistor resistor 1% wdosc r wdosc 34 120 k d 13.3 oscillator period r wdosc = 34k t osc 21.3 26.6 31.94 s a 13.6 oscillator period r wdosc = 120k t osc 68.4 85.6 102.8 s a 13.7 watchdog lead time after reset t d 3948 cycles b 13.8 watchdog closed window t 1 527 cycles b 13.9 watchdog open window t 2 553 cycles b 13.10 watchdog reset time nres nres t nres 2 4 6 ms b 7. electrical characteristics (continued) 5v < v vs < 28v, ?40c < t j < 150c; unless otherwise specified all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
ata663431/ata6634 54 [datasheet] 9232h?auto?09/14 28 14 watchdog trigger input pin ntrig 14.1 low-level voltage input ntrig v ntrig_l ?0.3 0.3v vcc v a 14.2 high-level voltage input ntrig v ntrig_h 0.7v vcc v vcc + 0.3 v a 14.3 pull-up resistor v ntrig =0v ntrig r ntrig 125 250 400 k a 14.4 input leakage current v ntrig =v vcc ntrig i ntrigleakh 1 a a 14.5 minimum trigger width v ntrig =v vcc ntrig t trig 200 ns d 15 mode pin 15.1 low-level input voltage mode v mode_l ?0.3 0.3v vcc v a 15.2 high-level input voltage mode v mode_h 0.7v vcc v vcc + 0.3 v a 15.4 leakage current v mode = 0v or v mode = v vcc mode i mode ?3 +3 a a 15.5 mode pin pull-up current v mode = 0.7v vcc mode i mode_pu ?75 ?5 a a 15.6 mode pin pull-down current v mode = 0.3v vcc mode i mode_pd 5 75 a a 16 limp home open drain failure output pin lh 16.1 output drain-to-source on resistance tj = 125c lh r dson,lh 50 a 16.2 leakage current v lh < 40v lh i leak,lh 2 a a 17 hsout pin 17.1 output drain-to-source on resistance i hsout = ?20ma hsout r dson,hs 20 a 17.2 leakage current ?0.2v < v hsout < v vs + 0.2v hsout i leak,hs 2 a a 17.5 switch-off slope (fall time) v vs = 16v r load = 560 c load = 1nf transition from 80% down to 20% of v vs hsout t hsslope,fall 0.75 5 s a 17.6 switch-on slope (rise time) v vs = 16v r load = 560 c load = 1nf transition from 20% to 80% of v vs hsout t hsslope,rise 0.75 5 s a 17.7 switch-on delay v vs = 16v r load = 560 c load = 1nf time from hsin=high to v hsout = 50% of v vs hsout t hsdel 3 20 s a 17.8 switch-off delay v vs = 16v r load = 560 c load = 1nf time from hsin=low to v hsout = 50% of v vs hsout t hsdel 3 20 s a 17.9 short-circuit detection threshold hsout v scth_hs v vs ? 6v v vs ? 2v v a 17.10 short-circuit deb. time hsout t hs_deb 2 10 s a 7. electrical characteristics (continued) 5v < v vs < 28v, ?40c < t j < 150c; unless otherwise specified all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
29 ata663431/ata66 3454 [datasheet] 9232h?auto?09/14 figure 7-1. definition of bus timing characteristics 18 hsin pin 18.1 low-level voltage input hsin v hsin_l ?0.3 0.3v vcc v a 18.2 high-level voltage input hsin v hsin_h 0.7v vcc v vcc + 0.3 v a 18.3 pull-down resistor v hsin = v vcc hsin r hsin 50 100 150 k a 18.4 low-level input current v hsin = 0v hsin i hsin ?1 +1 a a 18.5 maximum switching frequency r load = 560 hsin f hsin,max 5 khz d 19 cl15 hv input pin 19.1 high level input voltage positive edge initiates a local wake-up cl15 v cl15h 4 v a 19.2 low level input voltage cl15 v cl15l ?1 +2 v a 19.3 pull-down current v vs < 28v, v cl15 = 28v cl15 i cl15 50 60 a a 19.4 internal debounce time without external capacitor cl15 t dbcl15 50 100 150 s a 7. electrical characteristics (continued) 5v < v vs < 28v, ?40c < t j < 150c; unless otherwise specified all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter txd (input to transmitting node) vs (transceiver supply of transmitting node) rxd (output of receiving node1) rxd (output of receiving node2) lin bus signal thresholds of receiving node1 thresholds of receiving node2 t bus_rec(max) t rx_pdr(1) t rx_pdf(2) t rx_pdr(2) t rx_pdf(1) t bus_dom(min) t bus_dom(max) th rec(max) th dom(max) th rec(min) th dom(min) t bus_rec(min) t bit t bit t bit
ata663431/ata6634 54 [datasheet] 9232h?auto?09/14 30 8. application circuits figure 8-1. typical application circuit note: heat slug must always be connected to gnd. atmel ata663431 ata663454 dfn16 3 x 5.5 rxd en nres txd mode ntrig wdosc hsin vcc microcontroller vcc vbat master node pull-up vs lin gnd c3 220pf 10f/50v c2 100nf d1 c6 47nf c5 100nf c4 2.2f lin gnd wkin (opt.) cl15 (opt.) * the mode pin can be connected directly to gnd, if it is not needed to disable the watchdog es1 wkin lh cl15 hsout gnd 1 8 16 9 r8* 10k r1 10k 10k r4 10k r3 2.7k r2 1k d2 c1 r5 r6 51k vs vs 9. ordering information extended type number package remarks ata663431-gdqw dfn16 3.3v lin system basis chip, pb -free, 6k, taped and reeled ata663454-gdqw dfn16 5v lin system basis chip, pb -free, 6k, taped and reeled
31 ata663431/ata66 3454 [datasheet] 9232h?auto?09/14 10. package information package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title 6.543-5168.01-4 1 10/11/13 package: vdfn_5.5x3_16l exposed pad 4.7x1.6 two step singulation process common dimensions (unit of measure = mm) min nom note max symbol dimensions in mm specifications according to din technical drawings 0.035 0.05 0.0 a1 33.1 2.9 e 0.3 0.35 0.25 b 0.65 e 0.4 0.45 0.35 l 1.6 1.7 1.5 e2 4.7 4.8 4.6 d2 5.5 5.6 5.4 d 0.21 0.26 0.16 a3 0.85 0.9 0.8 a partially plated surface b l z 10:1 d 1 16 pin 1 id e top view a a3 a1 side view bottom view e d2 18 16 9 e2 z
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